Systematic encoder with arbitrary parity positions

ABSTRACT

An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested.

TECHNICAL FIELD

The present invention relates to an encoding circuit for datatransmission from a source to a destination over a communication channelby means of an error-correcting code.

BACKGROUND AND STATE OF THE ART

Reliable data transmission over a communication channel is fundamentalin all fields of information and communication technology.Unfortunately, most communication channels in the real world are noisy,so that the signal is distorted on its way from the sender to thereceiver. Signal distortions can be due both to imperfections of thesender and/or receiver equipment, or to external influences duringtransmission. Error-correcting codes have been developed to identify andcorrect such errors, so that, after correction, the recipient receives a(nearly) exact copy of the data transmitted by the sender with a highlevel of certainty. Typically, the particular code is chosen based onsome information about the infidelities of the channel through which thedata is transmitted, as well as the nature of the data.

A class of error-correcting codes with high practical relevance areReed-Solomon error-correcting codes, which protect messages byconstructing a polynomial from the raw data. The polynomial is evaluatedat several points, and these values are sent or recorded. Sampling thepolynomial more often than necessary makes the polynomialover-determined, and as long as the recipient receives sufficiently manyof these points correctly, she or he can recover the original polynomialeven in the presence of transmission errors. Reed-Solomon codes are usedin a wide variety of commercial applications, both for data storage onCDs, DVDs and blue ray discs as well as in broadcast systems such asdigital television. They are particularly efficient to protect againstburst errors, in which a whole train of subsequent data symbols iscorrupted.

Reed-Solomon error-correcting codes can be encoded as “systematiccodes”, i.e., the codeword contains the input data in its original formplus some parity symbols. The values of the parity symbols allow thedecoder to determine whether the data has been lost or corrupted duringtransmission, and to correct for transmission errors. In conventionalsystematic Reed-Solomon encoding schemes, a block of parity symbols issimply appended or pre-appended to the un-altered block of (raw) datasymbols.

In contrast, the upcoming ATSC mobile/handheld digital televisionstandard (ATSC-M/H) is based on a Reed-Solomon code in which the paritysymbols are no longer arranged in a block of consecutive symbols, butmay be spread arbitrarily within the codeword. Section 5.4.9 and TableA.1 of the specification “ATSC-M/H Standard, Part 2, RF/TransmissionSystem Characteristics (A/153, Part 2: 2009)”, published by the AdvancedTelevision Systems Committee, suggest a systematic t=10 error-correctingReed-Solomon code of length n=207 and dimension k=n−2×t=187 defined overthe finite field IF₂₅₆. The 2×t=20 parity symbols are supposed to beinserted according to one out of 118 different parity patterns, whichspecify the positions of the parity symbols in the codeword. Theseparity positions may differ from codeword to codeword. Conventionalencoding circuits are adapted to codewords in which the parity symbolsare arranged blockwise at fixed positions, and hence cannot be used toprovide codewords with arbitrary parity positions.

OBJECT OF THE PRESENT INVENTION

It is hence the object of the present invention to provide an encoderwhich allows to efficiently and quickly produce codewords with paritypositions according to any predefined parity pattern.

SUMMARY OF THE INVENTION

This objective is achieved by a method of encoding data with thefeatures of independent claim 1 as well as by providing an encoder withthe features of independent apparatus claim 11. The dependent claimsrelate to preferred embodiments.

The method of encoding data for transmission from a source to adestination over a communication channel by means of an error-correctingcode according to the present invention comprises the steps of receivinga plurality of data symbols and preparing at least one codeword of saiderror-correcting code at an encoding station, said codeword to betransmitted over said communication channel and comprising saidplurality of data symbols and a plurality of parity symbols. Said stepof preparing said codeword comprises the steps of selecting one out of aplurality of parity patterns, said parity pattern determining thepositions at which said parity symbols are located within said codeword,and determining said parity symbols on the basis of said data symbolsand said selected parity pattern, characterized in that determining atleast one of said parity symbols is based on a step of evaluating apolynomial of a degree that is no larger than the number of paritysymbols in said codeword.

It is the surprising finding of the present invention that the step ofdetermining the parity symbols at arbitrary parity positions can bereduced to the evaluation of a polynomial of a degree that is no largerthan the number of parity symbols. Evaluation of such a polynomial isfast, can be implemented efficiently and requires only very limitedhardware and storage capabilities. This allows the encoder to determinethe parity symbols and to produce the corresponding codewords fortransmission “on the fly”, i.e., as the data symbols are received by theencoder. As a result, the encoding rate, and hence the transfer rate atwhich signals can be sent from the receiver to the recipient can beenhanced. At the same time, the hardware and storage requirements forimplementing the encoder are reduced.

The present invention is not limited to Reed-Solomon codes, but iseffective at least whenever the error-correcting code is defined by aparity check matrix having a Vandermonde structure, i.e., whenever theparity check matrix H or its transpose satisfy the equation(H)_(ij)=a_(j) ^(i) for some set {a₀, a₁, . . . , a_(n-1)} of n distinctand nonzero elements of a finite field, i=0, . . . , 2·t−1; j=0, . . . ,n−1.

The present invention is equally effective when the parity check matrixcomprises a matrix having a Vandermonde structure, for example when theparity check matrix His a product H=V·Y, where V has a Vandermondestructure. The factor Y may be a diagonal matrix with non zero (but notnecessarily distinct) elements of the finite field. Codes defined by aparity check matrix of its form are sometimes called Alternant Codes.

According to a preferred embodiment, said polynomial is a Lagrangepolynomial, i.e.

$\begin{matrix}{{\Lambda^{(j)}\left( a_{i_{k}} \right)} = \left\{ \begin{matrix}{{{\frac{1}{y_{i_{j}}}\mspace{14mu}{for}\mspace{14mu} k} = j},} \\{{{0\mspace{14mu}{for}\mspace{14mu} k} \neq j},}\end{matrix} \right.} & (1)\end{matrix}$wherein {a₀, a₁, . . . , a_(n-1)} is a set of n distinct and non-zeroelements of a finite field the positive integer n denoting the length ofsaid codeword (c) {y₀, y₁, . . . , y_(n-1)} is a set of n non-zeroelements of a finite field, j is a positive integer denoting the paritysymbol, and i_(k) is a positive integer denoting the position of thek-th parity symbol in said codeword according to said selected paritypattern.

According to a preferred embodiment, y_(i) _(j) =1 for some or all y_(i)_(j) , 1 denoting a unit element of said field.

It is a finding of the present invention that the step of determiningsaid parity symbols can be reduced to the step of evaluating a Lagrangepolynomial. Due to the simple form of this polynomial, the efficiency ofdetermining the parity symbols can be further enhanced.

In a preferred embodiment, the j-th parity symbol can be determined byevaluating the equation

$\begin{matrix}{P_{j} = {\sum\limits_{\ell = 0}^{n - 1}{{\hat{c}}_{\ell} \cdot {{\Lambda^{(j)}\left( a_{\ell} \right)}.}}}} & (2)\end{matrix}$

for every parity symbol P_(j), where n denotes the length of saidcodeword, Λ^((j)) denotes a polynomial of a degree that is no largerthan the number of parity symbols in said codeword, {a₀, a₁, . . . ,a_(n-1)} is a set of n distinct and non-zero elements of a finite field,i_(k) is a positive integer denoting the position of the k-th paritysymbol in said codeword according to said selected parity pattern, andĉ_(l) equals the data symbol at position l of said codeword if l doesnot denote a position of a parity symbol in said codeword, or equals 0if l denotes a position of a parity symbol in said codeword.

According to a preferred embodiment, a_(k)=α^(k) for all k=0, . . . ,n−1, wherein α denotes a primitive element of said field. In thisembodiment, the columns of the parity check matrix Hare formed byforming the respective powers of n subsequent powers of the primitiveelement, i.e., (H)_(ij)=a^(i·j). A parity check matrix of this formcorresponds to a regular Reed-Solomon code, a very important class ofcodes. The method according to the present invention allows for aparticularly efficient determination of the parity symbols of regularReed-Solomon codes.

According to a further embodiment, said step of determining said paritysymbols comprises a step of evaluating said polynomial of a degree nolarger than the number of parity symbols, and further evaluating itsderivative, wherein said polynomial is independent of said paritysymbols.

It is the surprising finding of the inventors that the step ofdetermining said parity symbols can be based on the step of evaluating apolynomial which is one and the same for all the parity symbols to bedetermined. According to this embodiment, only a single polynomial needsto be evaluated to determine the plurality of parity symbols in saidcodeword. Accordingly, the speed and efficiency of the encoding circuitcan be further enhanced.

In a further embodiment, said step of determining said parity symbolscomprises a step of evaluating a ratio of said polynomial at an elementof a finite field and said element itself, and further evaluating saidderivative of said polynomial.

According to a preferred embodiment, said plurality of parity symbolsare solely defined in terms of the roots of said polynomial and theposition of the parity symbol within said codeword.

In further embodiment, the j-th parity symbol is determined byevaluating the equation

$\begin{matrix}{P_{j} = {\frac{1}{y_{i_{j}}}{\frac{1}{\Lambda^{\prime}\left( a_{i_{j}} \right)} \cdot {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{\Lambda\left( a_{l} \right)}{a_{l}} \cdot \frac{1}{1 - {a_{i_{j}}/a_{l}}}}}}}} & (3)\end{matrix}$for every parity symbol P_(j), wherein n denotes the length of saidcodeword (c), Λ denotes a polynomial of the degree that is no largerthan the number of parity symbols and said codeword (c), said polynomialΛ being independent of said parity symbols P_(j), {a₀, a₁, . . . ,a_(n-1)} is a set of n distinct and non-zero elements of a finite field,Λ′ denotes the first derivative of Λ, i_(j) is positive integer denotingthe position of the j-th parity symbol in said codeword, {y₀, y₁, . . ., y_(n-1)} is a set of n non-zero elements of a finite field, and ĉ_(l)equals the data symbol at position l of said codeword if l does notdenote a position of a parity symbol in said codeword, or equals 0 if ldenotes the position of a parity symbol in said codeword.

According to the latter embodiment, each parity symbol P_(j) can bedetermined by evaluating a polynomial Λ which is independent of theposition of the parity symbol in said codeword, and by furtherevaluating its derivative Λ′ on an element a_(i) _(j) that depends onthe position of the corresponding parity symbol in said codeword. Theremaining terms in Eq. (3) are likewise easy and quick to evaluate, andhence the step of determining the parity symbols reduces to a sequenceof standard operations for which an efficient implementation exists.

According to a preferred embodiment, said parity symbols are notarranged in a single block at the beginning or the end of said codeword.The method of the present invention allows to produce encryptedcodewords with parity symbols that may be spread arbitrarily within saidcodewords.

According to a further embodiment, said parity symbols are determined bymeans of a Chien search. A Chien search provides a very efficientarchitecture for evaluating said polynomial of a degree no larger than anumber of parity symbols in said codeword, and simultaneously evaluatingits derivative.

In an embodiment of the present invention, the method further comprisesa step of permuting the data symbols before preparing said codeword.

By permuting the data symbols, the step of determining the paritysymbols can be reduced to the determination of the parity symbols of acode with a simpler parity check matrix, for instance a parity checkmatrix of a regular Reed-Solomon code. As described above, the methodaccording to the present invention is particularly effective whendetermining parity symbols of a regular Reed-Solomon code. Hence,permutation of the code symbols allows to increase the efficiency ofdetermining the parity symbols of a generalized Reed-Solomon code oralternant code by reducing it to a regular Reed-Solomon code.

After the determination of the parity symbols, another permutation mayserve to restore the original order. Alternatively, the data symbols maybe sent over the communication channel in their permuted order, and maybe restored to their former order only at the receiving station(destination).

The invention also relates to a storage medium storing instructionsreadable by a computing device, such that the computing device, whenexecuting said instructions, implements a method with some or all of thefeatures described above.

The invention further relates to an encoder for encoding data to betransmitted from a source to a destination over a communication channelby means of an error-correcting code, said error-correcting code beingdefined by a parity check matrix having or comprising a Vandermondestructure, wherein said encoder comprises encoding means adapted toreceive a plurality of data symbols and to prepare at least one codewordof said error-correcting code, said codeword to be transmitted over saidcommunication channel and comprising said plurality of data symbols anda plurality of parity symbols. The encoder further comprises patternselection means adapted to select one out of a plurality of paritypatterns, said parity pattern determining the positions at which saidparity symbols are located within said codeword, characterized in thatsaid encoder is adapted to determine said parity symbols on the basis ofsaid data symbols and said selected parity pattern by evaluating apolynomial of a degree that is no larger than the number of paritysymbols in said codeword.

As described above, an encoder according to the present invention allowsthe quick and efficient encoding of codewords with arbitrary paritypositions.

According to a preferred embodiment, said encoder is adapted todetermine said parity symbols by evaluating said polynomial and furtherevaluating its derivative, said polynomial being independent of saidparity symbols.

In a further embodiment, said encoder is adapted to determine saidparity symbols by evaluating a ratio of said polynomial at an element ofa finite field and said element itself, and further evaluating saidderivative of said polynomial.

In a preferred embodiment, the encoder comprises a first summingcircuit, a second summing circuit, and a third summing circuit, saidthird summing circuit connecting an output line of said first summingcircuit to an output line of said second summing circuit, wherein saidfirst summing circuit comprises a plurality of first registers adaptedto hold a plurality of even powers of a primitive element of a finitefield and a corresponding number of first coefficients, said secondsumming circuit comprises a plurality of second registers adapted tohold a plurality of odd powers of said primitive element and acorresponding number of second coefficients, and said third summingcircuit is adapted to add an output of said first summing circuit to anoutput of said second summing circuit.

The encoder according to the latter embodiment takes into account thatboth the terms Λ(x)/x and Λ′(x) evaluated in determining the paritysymbols share monomials comprising the even powers of x. The circuitarchitecture according to the latter embodiment allows to evaluate theeven powers of the primitive element in the first summing circuit, andto simultaneously evaluate the odd powers in the second summing circuit.By adding an output of said first summing circuit to an output of saidsecond summing circuit in said third summing circuit, both termsrequired for evaluating the value of the parity symbols can be computedsimultaneously and with minimal resources, and the overall efficiency ofthe circuit is further enhanced.

Preferably, said first registers and/or said second registers eachcomprise a feedback loop for said even and odd powers of said primitiveelement, respectively.

By means of said feedback loop, said registers allow to compute thevalues of the polynomial

$\frac{\Lambda\left( \alpha^{l} \right)}{\alpha^{l}}$and Λ′(α^(l)) successively for each l=0, . . . , n−1, without having toreinitialize said registers. Consequently, the parity symbols can beevaluated faster and more efficiently.

According to a further embodiment, the encoder comprises a first summingcircuit, a second summing circuit, a third summing circuit, and aninitialization register. Said first summing circuit comprises aplurality of first registers adapted to hold a plurality of even powersof an element of a finite field and a corresponding number of firstcoefficients. Said second summing circuit comprises a plurality ofsecond registers adapted to hold a plurality of odd powers of saidelement and a corresponding number of second coefficients. Saidinitialization register is adapted to initialize said first registersand said second registers with said even and odd powers of said element,respectively, wherein said third summing circuit connects an output lineof said first summing circuit to an output line of said second summingcircuit, and is adapted to add an output of said first summing circuitto an output of said second summing circuit.

The initialization register allows to efficiently provide the codelocator elements to the respective summing circuit, and hence toevaluate said parity symbols even if the code locator elements a_(l) arenot consecutive powers of a primitive element α.

According to a further embodiment, said encoding means comprisesinterleaving means adapted to permute said data symbols before preparingsaid codeword.

As explained above, permuting said data symbols allows to reduce thedetermination of the parity symbols of a generalized Reed-Solomon codeor alternant code to the determination of the parity symbols of aregular Reed-Solomon code.

According to a further embodiment, the encoder comprises an inversioncircuit adapted to invert the output of said first summing circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The numerous features and advantages of the present invention will nowbe described with reference to the accompanying figures, in which:

FIG. 1 is a schematic circuit diagram illustrating the simultaneousevaluation of the parity locator polynomial and its derivative in aChien search according to a first embodiment of the present invention;

FIG. 2 is a schematic hardware circuit of an encoder according to thefirst embodiment;

FIG. 3 is a schematic circuit diagram illustrating the simultaneousevaluation of the parity locator polynomial and its derivative accordingto a second embodiment of the present invention;

FIG. 4 is a schematic hardware circuit of an encoder according to thesecond embodiment; and

FIG. 5 illustrates interleaving and deinterleaving means for permutingthe data symbols according to a third embodiment of the presentinvention.

The method and system according to the present invention are effectivewhenever data is to be transmitted from a source to a destination over acommunication channel by means of an error-correcting code defined by aparity check matrix having or comprising a Vandermonde structure. Theseinclude regular or generalized Reed-Solomon codes, alternant codes, BCHcodes as well as other codes based on Vandermonde-like parity checkmatrices. In particular, the invention may be applied to all codes whoseparity check matrix is a product of a Vandermonde matrix (or itstranspose) and a diagonal matrix.

The communication channel may model data transmission both through spaceand/or through time, such as data transmitted from one location toanother or data stored at one time and used at another. Channels inspace can be wires, networks, fibers, wireless media etc. between asender and a receiver. Channels in time can be data storage devices suchas CDs or DVDs. The channel is a description or model for thetransformation the data undergoes on its way from a source (or sender)to a destination (or receiver) separated in time and/or space.

For concreteness, the invention will now be described in further detailfor the example of a systematic regular Reed-Solomon code over a finitefield. However, it will be apparent to those skilled in the art that theinvention is not limited to such codes, and some exemplarygeneralizations will subsequently be discussed.

1. Definition of a Systematic Regular Reed-Solomon Code

Let {α⁰, α¹, . . . , α^(n-1)}ε IF_(q) be a set of n<q distinct andnonzero elements of a finite field IF_(q), where the positive integer qdenotes the size of the field IF_(q). A t-error-correcting Reed-Solomoncode (RS code) of length n and dimension k over the field IF_(q) may bedefined as

$\begin{matrix}{{C_{RS} = \left\{ {{{\underset{\_}{c} \in {{IF}_{q}^{n}\text{:}\mspace{14mu}{\sum\limits_{i = 0}^{n - 1}{c_{i}\alpha^{i \cdot j}}}}} = 0},\mspace{14mu}{j = 0},\ldots\mspace{14mu},{{2t} - 1}} \right\}},} & (4)\end{matrix}$where t and k are positive integers satisfying the relation 2t=n−k. Theelements α^(i)εIF_(q), i=0, . . . , n−1, are consecutive powers of theprimitive element α of IF_(q) and commonly called “code locators”. Indigital communications, the field size q is often restricted to powersof 2, so that all elements of IF_(q), q=2^(m), can be uniquelyrepresented by a vector of m bits.

For instance, the error-correcting code suggested for the upcoming ATSCmobile/handheld digital television standard is a systematic t=10error-correcting Reed-Solomon code of length n=207 and dimensionk=n−2·t=187, defined over the finite field IF₂₅₆. However, the methodand system according to the invention can be applied to codes of otherlengths n and other dimensions k.

As Reed-Solomon codes are linear block codes, they can be expressed asthe set of all vectors cεIF_(q) ^(n) lying in the null space (kernel) ofa parity check matrix H, i.e.,C _(RS) ={cεIF _(q) ^(n) :Hc ^(T)=0}.  (5)

The codeword c of total length n comprises k data symbols to betransmitted, as well as 2·t parity symbols used to identify and correcttransmission errors. A parity check matrix of this Reed-Solomon code,

$\begin{matrix}{{H = \begin{pmatrix}1 & 1 & 1 & \cdots & 1 \\\alpha^{0} & \alpha^{1} & \alpha^{2} & \cdots & \alpha^{n - 1} \\\vdots & \vdots & \vdots & \; & \vdots \\\alpha^{0 \cdot {({{2t} - 1})}} & \alpha^{1 \cdot {({{2t} - 1})}} & \alpha^{2 \cdot {({{2t} - 1})}} & \cdots & \alpha^{{({n - 1})} \cdot {({{2t} - 1})}}\end{pmatrix}},} & (6)\end{matrix}$is a 2t×n Vandermonde matrix, where each column h ^(T) _(i) consists of2t consecutive powers of the corresponding code locator element α^(i)for i=0, n−1. In matrix notation, (H_(ji))=a^(i·j) for the primitiveelement αεIF_(q); i=0, . . . , n−1; j=0, . . . , 2t−1.

For any linear code C there always exists an equivalent systematic codeC_(sys), producing codewords of the formC _(sys)=(I ₀ , I ₁ , . . . , I _(k-1) , P ₀ , P ₁ , . . . , P_(2t-1))  (7)where I_(l), l=0, k−1 denote k consecutive data symbols, and P_(j), j=0,. . . , 2t−1 denote the parity symbols of the codeword c _(sys). Eq. (7)represents codewords of a conventional RS code, in which all the paritysymbols are grouped into a single block, and are appended to the blockof data symbols. Alternatively, in a conventional RS code the block ofparity symbols may also be pre-appended to the block of data symbols.

Combining Equations (5) and (7), a systematic parity check matrixH_(sys) may be given the form,

$\begin{matrix}{{H_{sy}\left( {P❘I_{2t}} \right)}_{s}==\left( {P❘\begin{matrix}1 & \cdots & 0 \\\vdots & \ddots & \vdots \\0 & \cdots & 1\end{matrix}} \right)} & (8)\end{matrix}$where I_(2t) denotes a 2t×2t identity matrix. The submatrix P thatdefines the parity check relations can be found by translating theoriginal (non-systematic) parity check matrix H=1(A|B_(2t)) into itsequivalent systematic form H_(sys) by left-multiplying H with theinverse B_(2t) ⁻¹ of the submatrix B_(2t),H_(sys)=B_(2t) ⁻¹H, and hence P=B_(2t) ⁻¹A.  (9)

Due to its origin as a submatrix of H, B_(2t) is a 2t×2t Vandermondematrix as well. As long as the code locator elements α^(i) are distinctand nonzero, a Vandermonde matrix is of full rank and nonsingular.Consequently, B_(2t) will be nonsingular, and its inverse B_(2t) ⁻¹ willexist.

2. A Systematic Reed-Solomon Code with Arbitrary Parity Positions

According to the upcoming ATSC mobile/handheld digital televisionstandard, parity symbols may no longer be appended or pre-appended in asingle block to the block of data symbols, but may be located atarbitrary positions i_(j)ε[0, n−1], j=0, . . . 2t−1, within a codeword{tilde over (c)} _(RS), e.g.,{tilde over (c)} _(RS)=(I ₀ , I ₁ , . . . , P ₀ , . . . , P ₁ , . . . ,P _(2t-1) , . . . , I _(k-1)),  (10)

The set {i_(j)}_(j=0, . . . 2t-1) defines a parity pattern, i.e., a setof positions at which the parity symbols P_(j) are located within thecodeword {tilde over (c)} _(RS). Together with the data symbols, one ofa plurality of parity patterns {i_(j)}_(j=0, . . . 2t-1) is selected andreceived at the encoding station. The encoder then needs to determine acodeword {tilde over (c)} _(RS) with the selected parity pattern andhence its parity symbols (P_(j))_(j=0, . . . , 2t-1) on the basis of thedata symbols (I_(l))_(l=0, . . . , k-1) and the selected parity pattern{i_(j)}_(j=0, . . . , 2t-1). To this end, the parity check matrix can betransformed to the form

$\begin{matrix}{{\overset{\sim}{H} = \left( {P\mspace{14mu}\ldots\mspace{14mu}{\begin{matrix}1 \\0 \\\vdots \\0\end{matrix}}\mspace{14mu}\ldots\mspace{14mu} P^{\prime}\mspace{14mu}\ldots\mspace{14mu}{\begin{matrix}0 \\1 \\\vdots \\0\end{matrix}}\mspace{14mu}\ldots\mspace{14mu} P^{''}\mspace{14mu}\ldots\mspace{14mu}{\begin{matrix}0 \\0 \\\vdots \\1\end{matrix}}\mspace{14mu}\ldots\mspace{14mu} P^{\prime\prime\prime}} \right)}{{{code}\mspace{14mu}{locator}\mspace{14mu}{index}} = {i_{0}i_{l}i_{{2t} - 1}}}} & (11)\end{matrix}$where the locations i_(j) of the canonical unit vectors e _(j) within{tilde over (H)} specify the locations of the parity symbols P_(j)within the codeword {tilde over (c)} _(RS). As in Eq. (9) above, {tildeover (H)} can be expressed in terms of H and some matrix {tilde over(B)}, such that{tilde over (H)}={tilde over (B)}⁻¹H.  (12)

To satisfy this relationship, the matrix {tilde over (B)} must becomposed of the columns h _(i) ₀ ^(T), . . . , h _(i) _(2t-1) ^(T) ofthe original H, i.e.,

$\begin{matrix}\begin{matrix}{\overset{\sim}{B} = \begin{pmatrix}❘ & ❘ & \; & ❘ \\{\underset{\_}{h}}_{i_{0}}^{T} & {\underset{\_}{h}}_{i_{1}}^{T} & \cdots & {\underset{\_}{h}}_{i_{{2t} - 1}}^{T} \\❘ & ❘ & \; & ❘\end{pmatrix}} \\{= \begin{pmatrix}1 & 1 & \cdots & 1 \\\alpha^{i_{0}} & \alpha^{i_{1}} & \cdots & \alpha^{i_{{2t} - 1}} \\\vdots & \vdots & \; & \vdots \\\alpha^{i_{0} \cdot {({{2t} - 1})}} & \alpha^{i_{1} \cdot {({{2t} - 1})}} & \cdots & \alpha^{i_{{2t} - 1} \cdot {({{2t} - 1})}}\end{pmatrix}}\end{matrix} & (13)\end{matrix}$

From Eq. (13) it can be seen that {tilde over (B)} is again a 2t×2tVandermonde matrix consisting of distinct elements a^(i) ^(j) , thus itsinverse {tilde over (B)}⁻¹ is guaranteed to exist.

Based on these considerations, a rather straightforward (butinefficient) way of determining the parity symbols of a Reed-Solomoncode with arbitrary parity positions would be an inversion of thetransfer matrix {tilde over (B)} for each of the relevant paritypatterns. The parity check matrix {tilde over (H)} could then becomputed according to Eq. (12). However, the inversion of a (large)matrix {tilde over (B)} is computationally rather complex and requires alot of resources. It cannot be performed “on the fly”, as the datasymbols to be transmitted arrive at the encoder. Hence, the inverses{tilde over (B)}⁻¹ would need to be pre-computed and stored at theencoding station for each of the plurality of different parity patternsthat may be selected for encryption. There may be many different suchparity patterns. For instance, the ATSC-M/H Standard prescribes 118different patterns, resulting in total storage requirements of(118 patterns)×(187 columns/pattern)×(20 bytes/column)=441,320bytes.  (14)3. Efficient Determination of the Parity Symbols

As explained above, the two biggest obstacles in finding an efficientand compact encoder are the computationally very complex inversion of{tilde over (B)} on the one hand, and the storage requirements for{tilde over (H)} on the other. It is the surprising finding of thepresent invention that both obstacles can be circumvented by exploitingthe special Vandermonde structure of the parity check matrix. The ideais to make use of the fact that the inner product of some arbitraryvectora =(a ₀ , a ₁ , a ₂ , . . . a _(2t-1))εIF _(q) ^(2t)  (15)and a Vandermonde vector v, consisting of 2t consecutive powers of a^(i)^(j,)v=(1, α^(1·i) ^(j) , α^(2·i) ^(j) , . . . , α^((2t-1)·i) ^(j) )εIF _(q)^(2t)  (16)i.e.< a,v>=a ₀ +a ₁·α^(1·i) ^(j) +a ₂·α^(2·i) ^(j) + . . . +a_(2t-1)·α^((2t-1)·i) ^(j) =A(α ^(i) ^(j) ),  (17)is equivalent to the evaluation of a polynomial A(x)εIF_(q) [x] ofdegree 2t−1 and coefficient vector a with the element α^(i) ^(j) .IF_(q) [x] denotes the ring of polynomials with coefficients from thefield IF_(q).

The inner product of the j-th row of {tilde over (B)} ⁻¹, denoted byλ^((j)), and the l-th column h _(l) ^(T) of H results in<λ^((j)) ,h _(l)>=λ₀ ^((j))·1+λ₁ ^((j))·α^(l)+ . . . +λ_(2t-1)^((j))·α^(l·(2t-1))=Λ^((j))(α^(l)),  (18)and with this insight, Eq. (12) becomes

$\begin{matrix}\begin{matrix}{\overset{\sim}{H} = {{\overset{\sim}{B}}^{- 1}H}} \\{= \begin{pmatrix}\lambda_{0}^{(0)} & \lambda_{1}^{(0)} & \cdots & \lambda_{{2t} - 1}^{(0)} \\\lambda_{0}^{(1)} & \lambda_{1}^{(1)} & \cdots & \lambda_{{2t} - 1}^{(1)} \\\vdots & \vdots & \; & \vdots \\\lambda_{0}^{({{2t} - 1})} & \lambda_{1}^{({{2t} - 1})} & \cdots & \lambda_{{2t} - 1}^{({{2t} - 1})}\end{pmatrix}} \\{\begin{pmatrix}1 & 1 & \cdots & 1 \\\alpha^{0} & \alpha^{1} & \cdots & \alpha^{n - 1} \\\vdots & \vdots & \; & \vdots \\\alpha^{0 \cdot {({{2t} - 1})}} & \alpha^{1 \cdot {({{2t} - 1})}} & \cdots & \alpha^{{({n - 1})} \cdot {({{2t} - 1})}}\end{pmatrix}} \\{\begin{pmatrix}{\Lambda^{(0)}\left( \alpha^{0} \right)} & {\Lambda^{(0)}\left( \alpha^{1} \right)} & \cdots & {\Lambda^{(0)}\left( \alpha^{n - 1} \right)} \\{\Lambda^{(1)}\left( \alpha^{0} \right)} & {\Lambda^{(1)}\left( \alpha^{1} \right)} & \cdots & {\Lambda^{(1)}\left( \alpha^{n - 1} \right)} \\\vdots & \vdots & \; & \vdots \\{\Lambda^{({{2t} - 1})}\left( \alpha^{0} \right)} & {\Lambda^{({{2t} - 1})}\left( \alpha^{1} \right)} & \cdots & {\Lambda^{({{2t} - 1})}\left( \alpha^{n - 1} \right)}\end{pmatrix}}\end{matrix} & (19)\end{matrix}$

It hence remains to find the polynomials Λ^((j))(x)εIF_(q) [x],j=0, . .. , 2t−1, to determine {tilde over (H)}.

From Eq. (11) it can be seen that the columns {tilde over (h)} _(i) _(j)^(T) of {tilde over (H)} at the parity locations i_(j), j=0, . . . ,2t−1, reduce to canonical unit vectors {tilde over (e)} _(i) _(j) ^(T),

$\begin{matrix}{{{\overset{\sim}{\underset{\_}{h}}}_{i_{j}}^{T} = {\begin{pmatrix}{\Lambda^{(0)}\left( \alpha^{i_{j}} \right)} \\{\Lambda^{(1)}\left( \alpha^{i_{j}} \right)} \\\vdots \\{\Lambda^{({{2t} - 1})}\left( \alpha^{i_{j}} \right)}\end{pmatrix} = {\underset{\_}{e}}_{j}^{T}}},{{{where}\mspace{14mu}{\underset{\_}{e}}_{j}} = {\left( {\underset{\underset{j_{j}^{- 1}}{︸}}{0,\ldots\mspace{14mu},0},1,\underset{\underset{2_{{2t} - j - 1}^{t - i}}{︸}}{0,\ldots\mspace{14mu},0}} \right).}}} & (20)\end{matrix}$

Hence, for j=0, 2t-1, the polynomial Λ^((j))(x) is the j-th Lagrangepolynomial, i.e. the unique polynomial of degree 2t−1 from IF_(q)[x]satisfying

$\begin{matrix}{{\Lambda^{(j)}\left( \alpha^{i_{k}} \right)} = \left\{ \begin{matrix}1 & {{{{for}\mspace{14mu} k} = j},} \\0 & {{{for}\mspace{14mu} k} \neq {j.}}\end{matrix} \right.} & (21)\end{matrix}$

In order to find an expression for Λ^((j))(x), first let

$\begin{matrix}\begin{matrix}{{\Lambda(x)} = {\prod\limits_{j = 0}^{{2\; t} - 1}\;\left( {x - \alpha^{i_{j}}} \right)}} \\{= {\lambda_{0} + {\lambda_{1}x} + \ldots + {\lambda_{{2\; t} - 1}x^{{2\; t} - 1}} + x^{2\; t}}}\end{matrix} & (22)\end{matrix}$denote a monic polynomial of degree 2t in IF_(q) [x] with 2t roots α^(i)^(j) , j=0, . . . , 2t−1. As the index i_(j) defines the location of theparity symbol P_(j) within the codeword {tilde over (c)}_(RS) , theelements α^(i) ^(j) will be called “parity locators” and the polynomialΛ(x) “parity locator polynomial”. Using this parity locator polynomialΛ(x), the j-th Lagrange polynomial is given by

$\begin{matrix}\begin{matrix}{{\Lambda^{(j)}(x)} = \frac{\Lambda(x)}{\left( {x - \alpha^{i_{j}}} \right) \cdot {\Lambda^{\prime}\left( \alpha^{i_{j}} \right)}}} \\{{= {\lambda_{0}^{(j)} + {\lambda_{1}^{(j)}x} + \ldots + {\lambda_{{2\; t} - 1}^{(j)}x^{{2\; t} - 1}}}},}\end{matrix} & (23)\end{matrix}$where Λ′(x) denotes the formal derivative of Λ(x) in IF_(q) [x],

$\begin{matrix}\begin{matrix}{{\Lambda^{\prime}(x)} = {\sum\limits_{i = 1}^{2\; t}{i\;\lambda_{i}x^{i - 1}}}} \\{= {\lambda_{1} + {\lambda_{3}x^{2}} + {\lambda_{5}x^{4}} + \ldots + {\lambda_{{2\; t} - 1}{x^{{2\mspace{11mu} t} - 2}.}}}}\end{matrix} & (24)\end{matrix}$

The coefficients λ_(i) ^((j)); i, j=0, . . . , 2t−1, of the polynomialsΛ^((j))(x) from Eq. (23) completely determine the inverse {tilde over(B)}⁻¹ of the Vandermonde matrix {tilde over (B)}. In his researcharticle “Inverses of Vandermonde matrices”, The American MathematicalMonthly 71, No. 4 (1964) 410/411, Parker used a similar idea forefficiently inverting Vandermonde matrices.

An expression for the parity symbols P_(j) can now be found by combiningthe definition of Reed-Solomon codes given in Eq. (5) with the paritycheck matrix {tilde over (H)} from Eq. (19),{tilde over (C)} _(RS) ={cεIF _(q) ^(n) :{tilde over (H)}c^(T)=0}.  (25)

Since {tilde over (H)} arises from H by means of a left multiplicationwith the matrix of full rank, the null space condition can be verifiedeither for H or for {tilde over (H)}. Due to Eq. (20), each paritysymbol P_(j) will appear only in the inner product of the j-th row of{tilde over (H)} and the codeword c, resulting in a linear system ofequations,

$\begin{matrix}{{\overset{\sim}{C}}_{RS} = {\left\{ {{{\underset{\_}{c} \in {{IF}_{q}^{n}\text{:}\mspace{14mu}{\sum\limits_{l = 0}^{n - 1}{{\Lambda^{(j)}\left( \alpha^{l} \right)} \cdot c_{l}}}}} = 0},{j = 0},\ldots\mspace{14mu},{{2\; t} - 1}} \right\}.}} & (26)\end{matrix}$

In order to determine the parity symbols P_(j), we may define a modifiedcodeword vector

$\begin{matrix}{\mspace{146mu}{\hat{\underset{\_}{c}} = {{\left. \left( {I_{0},I_{1},0,0,I_{3},I_{4},\ldots\mspace{14mu},I_{k - 2},0,I_{k - 1}} \right)\mspace{239mu}\uparrow\mspace{14mu}\uparrow\mspace{169mu}\uparrow{code} \right.\mspace{14mu}{locator}\mspace{14mu}{index}} = {i_{0}\mspace{20mu} i_{1}\mspace{175mu} i_{{2\; t} - 1}}}}} & (27)\end{matrix}$whose l-th entry ĉ_(l) equals the data symbol at position l of thedesired codeword if l does not denote the position of a parity symbol insaid codeword, or equals zero if l denotes the position of a paritysymbol in said codeword. It is verified from Eq. (11) that the paritysymbols P_(j), j=0, . . . , 2t−1, can be calculated using the expression

$\begin{matrix}{P_{j} = {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot {{\Lambda^{(j)}\left( \alpha^{l} \right)}.}}}} & (28)\end{matrix}$

A codeword cεC_(RS) will then result from correctly combining the datavector I with the parity symbols P_(j) at the corresponding positionsi_(j). As apparent from Eq. (28), the determination of the parity symbolP_(j) can hence be reduced to the evaluation of a polynomial Λ^((j)) ofa degree that is no larger than the number of parity symbols in thecodeword. Compared with the brute force approach of inverting the matrix{tilde over (B)} in Eq. (13), this greatly simplifies the encoding: thestorage requirements are significantly reduced, and it becomes possibleto prepare codewords with parity symbols at arbitrary positions “on thefly”, i.e., as the codewords are received at the encoding station.

The surprising realization that the determination of the parity symbols,and thus the preparation of the codewords, can be reduced to a simpleevaluation of a polynomial of limited degree greatly enhances theefficiency of the encoding. It is a further finding of the inventorsthat the polynomial Λ^((j)) can be chosen as a Lagrange polynomial asdefined in Eq. (21) above. Due to it simplified structure, this allowsto further enhance the efficiency of the encoding circuit.

Plugging Eq. (23) into Eq. (28) leads to

$\begin{matrix}\begin{matrix}{P_{j} = {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{\Lambda\left( \alpha^{l} \right)}{\left( {\alpha^{l} - \alpha^{i_{j}}} \right) \cdot {\Lambda^{\prime}\left( \alpha^{i_{j}} \right)}}}}} \\{= {\frac{1}{\Lambda^{\prime}\left( \alpha^{i_{j}} \right)} \cdot {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{\Lambda\left( \alpha^{l} \right)}{\alpha^{l}} \cdot \frac{1}{1 - \alpha^{i_{j} - l}}}}}}\end{matrix} & (29)\end{matrix}$

The main advantage here is that the parity positions i, j=0, 2t-1, aresolely defined by the roots α^(i) ^(j) of the parity locator polynomialΛ(x), so it is sufficient to store the only 2·t coefficients from Eq.(22). The polynomial Λ is seen not to depend on the parity symbol P_(j),in the sense that Λ depends merely on the parity pattern{i_(j)}_(j=0, . . . , 2t-1) as a whole, but not on the respective parityposition i_(j) individually. As a result, the same polynomial Λ can beemployed to determine all the parity symbols P_(j) of a given paritypattern {i_(j)}_(j=0, . . . , 2t-1). This allows to further simplify thedetermination of the parity symbols and to reduce the storagerequirements. In the exemplary embodiment, it remains to store the2×t=20 coefficients of the parity locator polynomial Λ for each of the118 parity patterns under consideration. Hence, the storage requirementsare reduced to(118 patterns)×(20 coefficients/pattern)×(1 byte/coefficient)=2,360bytes.  (30)

Compared to the 441,320 bytes of the brute-force approach according toEq. (14), this amounts to a reduction by a factor of 187.

4. Hardware Implementation

A hardware implementation of an encoding circuit according to theforegoing embodiment of the present invention will now be described withreference to FIGS. 1 and 2.

An encoding station according to an embodiment of the inventionreceives, at a first input node, the data vector I=(I₀, I₁, . . . ,I_(k-1)) containing the k data symbols to be transmitted, and, at asecond node, the parity pattern {i_(j)}_(j=0, . . . , 2×t−)1 definingthe positions at which the parity symbols P_(j) are to be located withinthe codeword {tilde over (c)}_(RS) . As seen from Eq. (29), thefollowing terms are then required to calculate the parity symbols P_(j):

1. the data vector ĉ with zero-padded parity positions according to Eq.(27),

2. the term

$\frac{1}{1 - x}$for any non-zero value xεIF_(q),3. the term

$\frac{1}{\Lambda^{\prime}(x)},$evaluated at x=α^(i) ^(j) , j=0, . . . , 2t−1, as well as4. the term

$\frac{\Lambda(x)}{x},$evaluated at x=α^(l), l=0, . . . , n−1.

The values of the term

$\frac{1}{1 - x},$for x εIF_(q)\{0}, can be computed ahead of time and stored in an arrayof memory elements, for example in a shift register. Because each paritysymbol P_(j) evaluates this term at a different element x=α^(i) ^(j-l) ,all memory elements of such a shift register should preferably beaccessible at all times. Also, due to the arbitrary parity positionsi_(j) the sequence {α^(i) ^(j-l) }, l=0, . . . , n−1, may take on all qpossible non-zero values of the field IF_(q). Thus the shift registershould be of size q−1. Additionally, the register containing the elementwith exponent i_(j)-l=0 should preferably be set to 0 to preventnumerical instability and avoid additional logic switches.

The final step is to do an efficient evaluation of the terms

$\frac{1}{\Lambda^{\prime}(x)}$at x=α^(i) ^(j) , j=0, . . . , 2t−1 and

$\frac{\Lambda(x)}{x}$at x=α^(l), l=0, . . . , n−1. For finite fields IF_(q) with therestriction of the size q=2^(m), a comparison of the expressions for

$\begin{matrix}{\frac{\Lambda(x)}{x} = {{\lambda_{0}x^{- 1}} + \lambda_{1} + {\lambda_{2}x} + {\lambda_{3}x^{2}} + {\lambda_{4}x^{3}} + \ldots + {\lambda_{{2\; t} - 1}x^{{2\; t} - 2}} + {\lambda_{2\; t}x^{{2\; t} - 1}}}} & (31) \\{\mspace{79mu}{{\Lambda^{\prime}(x)} = {\lambda_{1} + {\lambda_{3}x^{2}} + \ldots + {\lambda_{{2\; t} - 1}x^{{2\; t} - 2}}}}} & (32)\end{matrix}$yields that both terms share monomials of the form λ_(2i+1)x^(2i) fori=0, t−1. As a result, the evaluation of the term Λ′(x) is a byproductof the evaluation of

$\frac{\Lambda(x)}{x}.$The value of Λ′(x) is then simply inverted to get the value of

$\frac{1}{\Lambda^{\prime}(x)} \cdot A$very efficient architecture for simultaneously evaluating Λ′(x) and

$\frac{\Lambda(x)}{x}$is a combined Chien search circuit as described in R. Chien, “CyclicDecoding Procedures for Bose-Chaudhuri-Hocquenghem Codes”, IEEETransactions on Information Theory, vol. 10, no. 4, pp. 357-363, October1964. If the memory elements are initialized with the coefficients λ₀, .. . , λ_(2t) of

$\frac{\Lambda(x)}{x},$this circuit will consecutively output the values of

$\frac{1}{\Lambda^{\prime}\left( \alpha^{\ell} \right)}\mspace{11mu}{and}\mspace{14mu}\frac{\Lambda\left( \alpha^{\ell} \right)}{\alpha^{\ell}}$for l=0, . . . , n−1 with each clock cycle.

A Chien circuit 10 for evaluating the parity locator polynomial and itsderivative is illustrated in FIG. 1. Circuit 10 comprises a firstsumming circuit 12 with a plurality of first registers 14, 14′, 14″,holding the even powers α², α⁴, α⁶ etc. of the primitive element α. Onlythree such first registers are shown in the illustration of FIG. 1.However, it is to be understood that the first summing circuit 12comprises a sufficient number of first registers for all the even powersup to α^(2t-2).

As shown in FIG. 1, in the first summing circuit 12 these even powersα², α⁴, α⁶ etc. are multiplied with the respective coefficients λ₃, λ₅,λ₇ etc. and are added to coefficient λ₁ to produce the value of thederivative Λ′(x) of the parity locator polynomial according to Eq. (32)at a first output line 16.

FIG. 1 further shows a second summing circuit 18 with a second pluralityof registers 20, 20′, 20″, 20′″ holding the odd powers α⁻¹, α¹, α³, α⁵etc. of the primitive element α. Only four such registers are depictedin the illustration of FIG. 1. However, it is to be understood that thesecond summing circuit comprises enough registers to store all of theodd powers necessary for the determination of Λ(x)/x according to Eq.(31) above. The odd powers α⁻¹, α¹, α³, α⁵ etc. are multiplied withrespective coefficients λ₀, λ₂, λ₄, λ₆ etc. and are added to produce anoutput at a second output line 22.

The third summing circuit 24 links the first output line 16 of the firstsumming circuit 12 to the second output line 22 of the second summingcircuit 18, and is adapted to add the output of the first summingcircuit 12 to the output of the second summing circuit 18. As isapparent from the description of the summing circuits as well as fromEq. (31) and (32), the third summing circuit 24 then outputs the valueof

$\frac{\Lambda(x)}{x}$at a third output line 26.

The architecture of the circuit thus makes efficient use of the factthat the terms

$\frac{\Lambda(x)}{x}$and Λ′(x) share monomials of the even powers of x, and hence allows toevaluate both terms simultaneously. As a result, the parity symbolsP_(j) can be evaluated more quickly, and hence more efficiently.

In the circuit shown in FIG. 1, each of the registers 14, 14′, 14″; 20,20′, 20″, 20′″ comprise a feedback loop 15, 15′, 15″, 21′, 21″, 21′″connecting the output of the register to the register input. By means ofthese feedback loops, the power of the element hold in the respectiveregisters is automatically increased in every register clock cycle.Hence, the terms

$\frac{\Lambda\left( \alpha^{\ell} \right)}{\alpha^{\ell}}$and Λ′ (α^(l)′) can be subsequently evaluated for l=0, . . . , n−1without reinitialization of the registers 14, 14′, 14″; 20, 20′, 20″,20′″, which saves both time and memory space.

A hardware circuit of an encoder according to an embodiment of thepresent invention will now be described with reference to FIG. 2. In theillustration of FIG. 2, reference numeral 10 denotes the combined Chiensearch circuit with first output line 16 and third output line 26, asdescribed previously with reference to FIG. 1. An inverter 58 appendedto the first output line 16 inverts the first output of the Chiencircuit 10 to produce

$\frac{1}{\Lambda^{\prime}\left( \alpha^{\ell} \right)}.$

The encoder further comprises a shift register block 28 in which thevalues

$\frac{1}{1 - \alpha^{i_{j} - \ell}}$are prestored and output on demand on a fourth output line 30 as well asan input node 32 for receiving the data vector I and a multiplier 34 formultiplying the value

$\frac{\Lambda\left( \alpha^{\ell} \right)}{\alpha^{\ell}}$with the corresponding element of input vector ĉ as defined in Eq. (27)above.

The encoder additionally has a plurality of parity locator circuits 36,36′ corresponding in number to the number 2t of parity symbols P_(j) inthe codeword. All these parity locator circuits share the samearchitecture, and hence FIG. 2 shows only two such circuits for the sakeof clarity. The circuits 36, 36′ comprise first input nodes 38, 38′connected to the output of the multiplier 34, second input nodes 40, 40′connected to the fourth output line 30, and third input nodes 42, 42′connected to the first output line 14 of the Chien search block 10. Byreading the respective outputs from the Chien search block 10 and theshift register 28 as well as from the multiplier 34, each of the paritylocator circuits 36, 36′ constitutes an implementation of Eq. (29) todetermine the corresponding parity symbol P_(j). The parity symbols

P₀, . . . , P_(2t-1) thus computed are output at output nodes 44, 44′,and are subsequently input, together with the data vector I₁, into acodeword buffer 46, which then yields the codeword vector c at an outputnode 48.

As can be seen by inspection of Eq. (29) as well as from theillustration of FIG. 2, each of the parity locator circuits 36, 36′ canbe implemented with merely two multipliers, one adder, and one selectionswitch each. A first multiplier 50, 50′is connected to the first inputnode 38, 38′ and the second input note 40, 40′, and is adapted tomultiply the output of the shift register 28 with the output ofmultiplier 34. The adder 54, 54′ is connected to the output of the firstmultiplier 50, 50′ and serves to compute the sum in Eq. (29). Theselection switch 56, 56′ selects the corresponding value from the firstoutput node 14 of the Chien search block 26, which is then multiplied atthe second multiplier 52, 52′ with the output of the adder 54, 54′ todetermine the parity symbol P_(j).

Since both the Chien search block 10 and the shift register 28 likewiserequire only standard components, the encoder according to the presentinvention is efficient in terms of hardware and memory and can be easilyimplemented both in an integrated circuit or in a hardwired design. Thehardware requirements for the implementation of a Reed-Solomon encoderaccording to an embodiment of the present invention are summarized inTable 1.

TABLE 1 Hardware Requirements Item Description Memory$q - {1\mspace{20mu}{registers}\mspace{20mu}{storing}\mspace{14mu}\frac{1}{1 - \alpha^{i_{j} - l}}}$2t + 1 registers in Chien search$2\; t\mspace{14mu}{registers}\mspace{14mu}{storing}\mspace{14mu}{the}\mspace{14mu}{values}\mspace{14mu}\frac{1}{\Lambda^{\prime}\left( \alpha^{i_{j}} \right)}$2t registers in summation n registers for codeword buffer Adders 2tadders in Chien search 2t adders in summation Multipliers 2t constantmultipliers in Chien search 2t + 1 variable multipliers for paritysymbols 2t variable multipliers for normalization Inverters$1\mspace{14mu}{inverter}\mspace{14mu}{for}\mspace{14mu}\frac{1}{\Lambda^{\prime}\left( \alpha^{i_{j}} \right)}\mspace{14mu}{after}\mspace{14mu}{Chien}{\mspace{11mu}\;}{search}$Logic Switches$2t\mspace{14mu}{logic}\mspace{14mu}{switches}{\mspace{11mu}\;}{to}\mspace{14mu}{select}\mspace{14mu}\frac{1}{\Lambda^{\prime}\left( \alpha^{i_{j}} \right)}$5. Generalized Reed-Solomon Codes and Alternate Codes

As will now be described in additional detail, the determination of theparity check symbols P_(j) can be generalized with only minor amendmentsto the larger classes of alternant codes and generalized Reed-Solomoncodes. In these generalizations, the determination of the parity symbolscan likewise be reduced to the step of evaluating a polynomial of adegree that is no larger than the number of parity symbols in thecodeword, and hence the same advantages over the prior art result.

Let a={a₀, a₁, . . . , a_(n-1)} εIF_(q) be a set of n≦_(q) distinct andnonzero elements of a finite field IF_(q), where q is again the size ofthe field. Let y={y₀, y₁, . . . , y_(n-1)} denote a set of n nonzero(but not necessarily distinct) elements of IF_(q). A t-error-correctingGeneralized Reed-Solomon code of length n and dimension k=n−2t over thefield IF_(q) may be defined as

$\begin{matrix}{{C_{GRS}\left( {{IF}_{q},n,t,\underset{\_}{a},\underset{\_}{y}} \right)} = {\left\{ {{{\underset{\_}{c \in {{IF}_{q}^{n}:\sum\limits_{i = 0}^{n - 1}}}y_{i}c_{i}a_{i}^{j}} = 0},{j = 0},\ldots\mspace{14mu},{{2t} - 1}} \right\}.}} & (33)\end{matrix}$

Regular Reed-Solomon codes described previously with respect to thefirst embodiment correspond to the special case wherein the codelocators a_(i) satisfy the equation a_(i)=α^(j) for some primitiveelement a of the field IF_(q) for all i=0, . . . , n−1, and y_(i)=1 forall i=0, . . . , n−1.

As before, we can also define Generalized Reed-Solomon codes as the setof all vectors c lying in the null space (kernel) of a parity checkmatrix H_(GRS), i.e.,GRS(IF _(q) ,n,t,a,y )={ cεIF _(q) ^(n) :H _(GRS) c ^(T)=0}.  (34)

It is seen from Eq. (33) that the parity check matrix H_(GRS) of ageneralized Reed-Solomon code may be written as a product H=V·Y,

$\begin{matrix}{{H_{GRS} = {{\begin{pmatrix}1 & 1 & 1 & \ldots & 1 \\a_{0} & a_{1} & a_{2} & \ldots & a_{n - 1} \\\vdots & \vdots & \vdots & \; & \vdots \\a_{0}^{{2t} - 1} & a_{1}^{{2t} - 1} & a_{2}^{{2t} - 1} & \ldots & a_{n - 1}^{{2t} - 1}\end{pmatrix}\begin{pmatrix}y_{0} & 0 & \ldots & 0 \\0 & y_{1} & \ldots & 0 \\\vdots & \; & \ddots & \vdots \\0 & 0 & \ldots & y_{n - 1}\end{pmatrix}} = {VY}}},} & (35)\end{matrix}$where the matrix V is a 2t×n Vandermonde matrix, whose (i+1)th columnv_(i) ^(T) consists of 2t consecutive powers of the corresponding codelocator element a_(i) for i=0, . . . , n−1. Y as an (n×n) diagonalmatrix with non-zero (but not necessarily distinct) diagonal elementsy_(i).

As described for the first embodiment, the generalized parity checkmatrix H_(GRS) can again be transformed into the canonical form {tildeover (H)}_(GRS) of Equation (11) by means of multiplication with theinverse of some matrix {tilde over (B)},{tilde over (H)} _(GRS) ={tilde over (B)} ⁻¹ ·{tilde over (H)} _(GRS)={tilde over (B)} ⁻¹ ·V·Y  (36)

Since V is a Vandermonde matrix and y_(i)≠0 for all i=0, . . . , n−1,{tilde over (B)}⁻¹ is again guaranteed to exist. Defining λ_(i)^(j)=({tilde over (B)}⁻¹)_(ji) for i, j=0, . . . , 2t−1 as in Eq. (19)and the polynomialsΛ^((j))(a _(l))=λ₀ ^((j))·1+λ₁ ^((j)) ·a _(l)+ . . . +λ_(2t-1) ^((j)) a_(l) ^(2t-1)  (37)as in Eq. (18), we see from Eq. (36) and Eq. (11) that

$\begin{matrix}{{\Lambda^{(j)}\left( a_{i_{k}} \right)} = \left\{ \begin{matrix}\frac{1}{y_{i_{j}}} & {{{{for}\mspace{14mu} k} = j},} \\0 & {{{{for}\mspace{14mu} k} \neq j},}\end{matrix} \right.} & (38)\end{matrix}$where the integers i_(j), j=0, . . . , 2−1 denote the positions of theparity symbols P_(j) within the codeword c. The non-zero coefficientsy_(i) _(j) ,j=0, . . . , 2·−1 take care of the multiplication by thematrix Y in the definition of the generalized parity check matrixH_(GRS) in Eq. (36). Defining the parity locator polynomial

$\begin{matrix}\begin{matrix}{{\Lambda(x)} = {\prod\limits_{j = 0}^{{2t} - 1}\left( {x - a_{i_{j}}} \right)}} \\{= {\lambda_{0} + {\lambda_{1}x} + \ldots + {\lambda_{{2t} - 1}x^{{2t} - 1}} + x^{2t}}}\end{matrix} & (39)\end{matrix}$we then have

$\begin{matrix}{{{\Lambda^{(j)}(x)} = {\frac{1}{y_{i_{j}}} \cdot \frac{\Lambda(x)}{\left( {x - a_{i_{j}}} \right) \cdot {\Lambda^{\prime}\left( a_{i_{j}} \right)}}}},} & (40)\end{matrix}$where Λ′ again denotes the formal derivative of Λ.

Defining the modified codeword vector ĉ as in Eq. (27) above, the paritysymbol P_(j) may then be given the expression

$\begin{matrix}\begin{matrix}{P_{j} = {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{1}{y_{i_{j}}} \cdot \frac{\Lambda\left( a_{l} \right)}{\left( {a_{l} - a_{i_{j}}} \right) \cdot {\Lambda^{\prime}\left( a_{i_{j}} \right)}}}}} \\{= {\frac{1}{y_{i_{j}}} \cdot \frac{1}{\Lambda^{\prime}\left( a_{i_{j}} \right)} \cdot {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{\Lambda\left( a_{l} \right)}{a_{l}} \cdot {\frac{1}{1 - {a_{i_{j}}/a_{l}}}.}}}}}\end{matrix} & (41)\end{matrix}$

As can be seen from a comparison of Equations (40) and (29), theexpression for the parity symbol P_(j) according to the secondembodiment reduces to Eq. (29) by setting y_(i) _(j) =1 for all j=0, . .. , 2·t−1 and a_(k)=α^(k) for each k=0, . . . , n−1. While being ageneralization of the first embodiment, inspection of Eq. (40) showsthat the method according to the second embodiment still allows tocompute the parity symbols by evaluating a polynomial Λ of a degree thatis no larger than the number of parity symbols in the codeword. Asdescribed above for the previous embodiment, this allows for asimplified determination of the parity symbols and a substantialreduction of the storage requirements.

From Eq. (40), we see that the following terms are required to calculatethe parity symbol P_(j),

1. the data vector ĉ, with zero-padded parity positions according to Eq.(27),

2. the term

$\frac{1}{1 - x}$for any non-zero value of xεIF_(q),3. the values

$\frac{1}{y_{i_{j}}}$for j=0, . . . , 2t−1,4. the term

$\frac{1}{\Lambda^{\prime}(x)},$evaluated at x=a_(i) _(j) , j=0, . . . , 2t−1, as well as5. the term

$\frac{\Lambda(x)}{x},$evaluated at x=a_(l), l=0, . . . , n−1

The parity symbols P_(j) can hence be determined in a hardwareimplementation of an encoding circuit that is very similar to theencoding described with reference to the first embodiment in Section 4above. A generalized Chien circuit 10′ for evaluating the paritypolynomial and its derivative according to the method of the secondembodiment is illustrated in FIG. 3. The circuit largely corresponds tothe one depicted in FIG. 1, and like elements share the same referencenumerals.

The initialization register 60 receives the code locator element a_(l)via an input line 62, and creates and holds the powers a_(l) ⁻¹, a_(l),. . . , a_(l) ^(2t-1). The even powers are then loaded into theregisters 14, 14′, 14″ of the first summing circuit 12 by means of firstoutput lines 64 of the initialization register 60, while the odd powersare transferred to the registers 20, 20′, 20″, 20′″ of the secondsumming register 18 via second output lines 66.

The circuit 10′ then proceeds to compute Λ′(a_(l)) at the first outputline 16 and

$\frac{\Lambda\left( a_{l} \right)}{a_{l}}$at the third output line 26, just as described with reference to FIG. 1above.

Afterwards, the initialization register 60 can be provided with anothercode locator element, and so forth for all code locator elements a_(l),l=0, . . . , n−1. Since the first and second registers are consecutivelyinitialized with the respective code locator element, the feedback loops15, 15′, 15″ and 21, 21′, 21″, 21″, respectively, shown in FIG. 1 anddescribed with reference to the first embodiment are no longer required.

The hardware circuit of an encoder according to the second embodimentwill now be described with reference to FIG. 4. The hardware circuitemploys the generalized Chien search block 10′ instead of the Chiensearch block 10, but is otherwise very similar to the hardware circuitof the first embodiment, as described previously with reference to FIG.2. Corresponding elements will again be denoted by the same referencesigns, and their description will be omitted in order to avoidunnecessary duplication.

Besides the shift register 28 for storing the values

$\frac{1}{1 - {a_{i_{j}}/a_{l}}},$the encoder circuit further comprises a second shift register block 68for storing the multipliers

$\frac{1}{y_{l}}.$

The parity locator circuits 36, 36′ are adapted accordingly andadditionally comprise fourth input nodes 70, 70′, respectively, forconnection to the second shift register block 68, as well as secondselection switches 72, 72′ for selecting the corresponding value

$\frac{1}{y_{i_{j}}}$and multiplying it with the output of the adder 54, 54′ at thirdmultipliers 74, 74′. The parity locator circuit 36, 36′ then outputs thecorresponding parity symbol P_(j) according to Eq. (40) at therespective output node 44, 44′. The parity symbols P₀, . . . , P_(2t-1)thus determined are input, together with the data vector I_(l) receivedat data input node 32, into the codeword buffer 46, which yields thecodeword vector c at output node 48.

A comparison of FIG. 4 with FIG. 2 shows that the generalized encodercircuit according to the second embodiment, despite being adapted toaccommodate a much larger class of codes, requires only a slightlylarger number of components, namely an initialization register 60, asecond shift register block 68 for storing the multipliers

$\frac{1}{y_{l}},$and an additional selection switch 72 and multiplier 74 for each paritylocator circuit 36, 36′. Since these are again standard components, theencoder according to the second embodiment likewise provides a veryefficient implementation for determining codewords with parity symbolsat arbitrary parity locations.6. Generalized Reed-Solomon Codes by Interleaving

According to a third embodiment of the present invention, thedetermination of the parity symbols for a generalized Reed-Solomon codeas defined in Eq. (33) can be reduced to the determination of paritysymbols for a regular Reed-Solomon code. This approach exploits theproperty that the base elements a₀, a₁, . . . , a_(n-1) of theVandermonde matrix Vas defined in Eq. (35) are a subset of all q−1possible nonzero elements of the finite field IF_(q), albeit in noparticular order. Hence, there exists a column permutation matrixP_(Perm), such that

$\begin{matrix}\begin{matrix}{V = \begin{pmatrix}1 & 1 & 1 & \ldots & 1 \\a_{0} & a_{1} & a_{2} & \ldots & a_{n - 1} \\\vdots & \vdots & \vdots & \; & \vdots \\a_{0}^{{2t} - 1} & a_{1}^{{2t} - 1} & a_{2}^{{2t} - 1} & \ldots & a_{n - 1}^{{2t} - 1}\end{pmatrix}} \\{= {\begin{pmatrix}1 & 1 & 1 & \ldots & 1 \\\alpha^{0} & \alpha^{1} & \alpha^{2} & \ldots & \alpha^{q - 2} \\\vdots & \vdots & \vdots & \; & \vdots \\\alpha^{0 \cdot {({{2t} - 1})}} & \alpha^{0 \cdot {({{2t} - 1})}} & \alpha^{0 \cdot {({{2t} - 1})}} & \ldots & \alpha^{{({q - 2})} \cdot {({{2t} - 1})}}\end{pmatrix} \cdot}} \\{\begin{pmatrix}{\left( {q - 1} \right) \times n\mspace{14mu}{Column}} \\{{Permutation}\mspace{14mu}{Matrix}}\end{pmatrix}} \\{= {\overset{\sim}{V} \cdot P_{Perm}}}\end{matrix} & (42)\end{matrix}$

The matrix {tilde over (V)} with base elements {1, . . . , α, q−2} isagain a Vandermonde matrix, and corresponds to the parity check matrixof a regular Reed-Solomon code with code length n=q−1, as described inSection 1. Combining Eq. (42) with Eq. (35), we see thatH_(GRS)={tilde over (V)}P_(Perm)Y.  (43)

We may hence employ an encoder circuit according to the firstembodiment, provided the input vector I is permuted and padded so thatit corresponds to the input vectors of a regular Reed-Solomon code ofcode length n=q−1. Once the encoding is completed, the permutation maybe reversed to restore the original order, and the codeword symbols maybe multiplied by the corresponding elements y_(i) of Y.

An encoding circuit according to the third embodiment comprising aninterleaving circuit 76 and a deinterleaving circuit 78 will now bedescribed with reference to FIG. 5.

The interleaving circuit 76 comprises an input register 76 a of length nto hold the input data vector I, and an output register 76 b of lengthq−1, which is initialized with zeros. The interleaving circuit 76 isadapted to permute and pad the input data vector I according to thepermutation matrix P_(Perm). The resulting (permuted) input data vectorII(I) is then encoded with an encoding circuit 80 for a regularReed-Solomon code of code length n, for instance an encoding circuitaccording to the first embodiment, as described with reference to FIGS.1 and 2 above. The encoding by means of encoding circuit 80 results in acodeword II(c) of length q−1, which can then be reduced to the originallength n by deinterleaving with the permutation matrixes P_(Perm) atdeinterleaving means 78. Deinterleaving means 78 comprise an inputregister 78 a of length q−1 for holding the interleaved and paddedcodeword II(c) generated by the encoding circuit 80, as well as anoutput register 78 b of length n for holding the resulting codeword c,which is obtained from II(c) by inversing the permutation P_(Perm) andby multiplying the parity symbols P_(j) with the correspondingcoefficients

$\frac{1}{y_{i_{j}}}.$The codeword c of the generalized Reed-Solomon code with arbitraryparity positions is then output at an output line 82, and maysubsequently be sent over a communication channel.

According to the third embodiment, codewords of a generalizedReed-Solomon code with arbitrary parity positions may be generated bymeans of an encoding circuit 80 for a regular Reed-Solomon code, whichrequires less hardware and computational resources than the encodingcircuit described with reference to FIGS. 3 and 4. The method accordingto the third embodiment is particularly advantageous whenever the codelength n is not much smaller than the field size q−1.

The description and the figures merely serve to illustrate the inventionand its numerous advantages, and should not be understood to restrict orlimit the invention in any way. The scope of the invention is determinedsolely by the appended set of claims.

REFERENCE SIGNS

-   10, 10′ Chien search block-   12 first summing circuit-   14, 14′, 14″ first registers-   15, 15′, 15″ feedback loops of the first registers 14, 14′, 14″-   16 first output line-   18 second summing circuit-   20, 20′, 20″, 20′″ second registers-   21, 21′, 21″, 21′″ feedback loops of the second registers 20, 20′,    20″, 20′″-   22 second output line-   24 third summing circuit-   26 third output line-   28 shift register block-   30 fourth output line-   32 data input node-   34 multiplier-   36, 36′ parity locator circuits-   38, 38′ first input nodes of parity locator circuits 36, 36′-   40, 40′ second input nodes of parity locator circuits 36, 36′-   42, 42′ third input nodes of parity locator circuits 36, 36′-   44, 44′ output nodes of parity locator circuits 36, 36′-   46 codeword buffer-   48 output node of codeword buffer 46-   50, 50′ first multiplier of parity locator circuit 36, 36′-   52, 52′ second multiplier of parity locator circuit 36, 36′-   54, 54′ adder of parity locator circuit 36, 36′-   56, 56′ selection switch of parity locator circuit 36, 36′-   58 inversion circuit-   60 initialization register-   62 input line of the initialization register 60-   64 first output lines of the initialization register 60-   66 second output lines of the initialization register 60-   68 second shift register block-   70, 70′ fourth input nodes of parity locator circuit 36, 36′-   72, 72′ second selection switch of parity locator circuit 36, 36′-   74, 74′ third multiplier of parity locator circuit 36, 36′-   76 interleaving circuit-   76 a input register of interleaving circuit 76-   76 b output register of interleaving circuit 76-   78 deinterleaving circuit-   78 a input register of deinterleaving circuit 78-   78 b output register of deinterleaving circuit 78-   80 encoding circuit-   82 output line

1. A method of encoding data for transmission from a source to adestination over a communication channel by means of an error-correctingcode, said error-correcting code being defined by a parity check matrix(H) having or comprising a Vandermonde structure, the method comprisingthe steps of: receiving a plurality of data symbols (I_(l)); andpreparing at least one codeword (c) of said error-correcting code at anencoding station, said codeword to be transmitted over saidcommunication channel and comprising said plurality of data symbols(I_(l)) and a plurality of parity symbols (P_(j)); wherein said step ofpreparing said codeword (c) comprises the steps of: selecting one out ofa plurality of parity patterns ({i_(j)}_(j=0, . . . , 2t-1)), saidparity pattern ({i_(j)}_(j=0, . . . , 2t-1)) determining the positionsat which said parity symbols (P_(j)) are located within said codeword(c); and determining said parity symbols (P_(j)) on the basis of saiddata symbols (I_(l)) and said selected parity pattern({i_(j)}_(j=10, . . . , 2t-1)); characterized in that determining atleast one of said parity symbols (P_(j)) is based on a step ofevaluating a polynomial (Λ^((j)), Λ) of a degree that is no larger thanthe number of parity symbols (P_(j)) in said codeword (c); wherein saidpolynomial (Λ^((j))) is a Lagrange polynomial, i.e.,${\Lambda^{(j)}\left( a_{i_{k}} \right)} = \left\{ \begin{matrix}\frac{1}{y_{i_{j}}} & {\;{{{fork} = j},}} \\0 & {{{fork} \neq j},}\end{matrix} \right.$ wherein {a₀, a₁, . . . , a_(n-1)} is a set of ndistinct and non-zero elements of a finite field, the positive integer ndenoting the length of said codeword (c), {y₀, y₁, . . . , y_(n-1)} is aset of n non-zero elements of said finite field, j is a positive integerdenoting the parity symbol, and i_(k) is a positive integer denoting theposition of the k-th parity symbol in said codeword according to saidselected parity pattern.
 2. The method according to claim 1, whereiny_(i) _(j) =1 for some or all y_(i) _(j) , l denoting a unit element ofsaid field.
 3. The method according to claim 1, wherein a_(k)=a^(k) forall k=0, . . . , n-1, α denoting a primitive element of said field. 4.The method according to claim 1, wherein said plurality of paritysymbols (F_(j)) are solely defined in terms of the roots of saidpolynomial (Λ) and the position of the parity symbol within saidcodeword.
 5. The method of claim 1, further comprising a step ofpermuting said data symbols (I_(l)) before preparing said codeword (c).6. A method of encoding data for transmission from a source to adestination over a communication channel by means of an error-correctingcode, said error-correcting code being defined by a parity check matrix(H) having or comprising a Vandermonde structure, the method comprisingthe steps of: receiving a plurality of data symbols (I_(l)); andpreparing at least one codeword (c) of said error-correcting code at anencoding station, said codeword to be transmitted over saidcommunication channel and comprising said plurality of data symbols(I_(l)) and a plurality of parity symbols (P_(j)); wherein said step ofpreparing said codeword (c) comprises the steps of: selecting one out ofa plurality of parity patterns ({i_(j)}_(j=0, . . . , 2t-1)), saidparity pattern ({i_(j)}_(j=0, . . . , 2t-1)) determining the positionsat which said parity symbols (P_(j)) are located within said codeword(c); and determining said parity symbols (P_(j)) on the basis of saiddata symbols (I_(l)) and said selected parity pattern({i_(j)}_(j=0, . . . , 2t-1)); characterized in that determining atleast one of said parity symbols (P_(j)) is based on a step ofevaluating a polynomial (Λ^((j)), Λ) of a degree that is no larger thanthe number of parity symbols (P_(j)) in said codeword (c); wherein thej-th parity symbol is determined by evaluating the equation$P_{j} = {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot {\Lambda^{(j)}\left( a_{l} \right)}}}$for every parity symbol P_(j), wherein n denotes the length of saidcodeword (c), Λ^((j)) denotes a polynomial of a degree that is no largerthan the number of parity symbols in said codeword (c), {a₀, a₁, . . . ,a_(n-1)} is a set of n distinct and non-zero elements of a finite field,and ĉ_(l) equals the data symbol at position l of said codeword (c) if ldoes not denote a position of a parity symbol in said codeword (c), orequals 0 if l denotes a position of a parity symbol in said codeword(c).
 7. The method according to claim 6, wherein said plurality ofparity symbols (P_(j)) are solely defined in terms of the roots of saidpolynomial (Λ) and the position of the parity symbol within saidcodeword.
 8. The method of claim 6, further comprising a step ofpermuting said data symbols (I_(l)) before preparing said codeword (c).9. A method of encoding data for transmission from a source to adestination over a communication channel by means of an error-correctingcode, said error-correcting code being defined by a parity check matrix(H) having or comprising a Vandermonde structure, the method comprisingthe steps of: receiving a plurality of data symbols (I_(l)); andpreparing at least one codeword (c) of said error-correcting code at anencoding station, said codeword to be transmitted over saidcommunication channel and comprising said plurality of data symbols(I_(l)) and a plurality of parity symbols (P_(j)); wherein said step ofpreparing said codeword (c) comprises the steps of: selecting one out ofa plurality of parity patterns ({i_(j)}_(j=0, . . . , 2t-1)), saidparity pattern ({i_(j)}_(j=0, . . . , 2t-1)) determining the positionsat which said parity symbols (P_(j)) are located within said codeword(c); and determining said parity symbols (P_(j)) on the basis of saiddata symbols (I_(l)) and said selected parity pattern({i_(j)}_(j=0, . . . , 2t-1)); characterized in that determining atleast one of said parity symbols (P_(j)) is based on a step ofevaluating a polynomial (Λ^((j)), Λ) of a degree that is no larger thanthe number of parity symbols (P_(j)) in said codeword (c); wherein saidstep of determining said parity symbols (P_(j)) comprises a step ofevaluating said polynomial (Λ), and further evaluating its derivative(Λ′), said polynomial (Λ) being independent of said parity symbols(P_(j)).
 10. The method according to claim 9, wherein said plurality ofparity symbols (P_(j)) are solely defined in terms of the roots of saidpolynomial (Λ) and the position of the parity symbol within saidcodeword.
 11. The method of claim 9, further comprising a step ofpermuting said data symbols (I_(l)) before preparing said codeword (c).12. A method of encoding data for transmission from a source to adestination over a communication channel by means of an error-correctingcode, said error-correcting code being defined by a parity check matrix(H) having or comprising a Vandermonde structure, the method comprisingthe steps of: receiving a plurality of data symbols (I_(l)); andpreparing at least one codeword (c) of said error-correcting code at anencoding station, said codeword to be transmitted over saidcommunication channel and comprising said plurality of data symbols(I_(l)) and a plurality of parity symbols (P_(j)); wherein said step ofpreparing said codeword (c) comprises the steps of: selecting one out ofa plurality of parity patterns ({i_(j)}_(j=0, . . . , 2t-1)), saidparity pattern ({i_(j)}_(j=0, . . . , 2t-1)) determining the positionsat which said parity symbols (P_(j)) are located within said codeword(c); and determining said parity symbols (P_(j)) on the basis of saiddata symbols (I_(l)) and said selected parity pattern({i_(j)}_(j=0, . . . , 2t-1)); characterized in that determining atleast one of said parity symbols (P_(j)) is based on a step ofevaluating a polynomial (Λ^((j)), Λ) of a degree that is no larger thanthe number of parity symbols (P_(j)) in said codeword (c); wherein thej-th parity symbol (P_(j)) is determined by evaluating the equation$P_{j} = {\frac{1}{y_{i_{j}}}{\frac{1}{\Lambda^{\prime}\left( a_{i_{j}} \right)} \cdot {\sum\limits_{l = 0}^{n - 1}{{\hat{c}}_{l} \cdot \frac{\Lambda\left( a_{l} \right)}{a_{l}} \cdot \frac{1}{1 - {a_{i_{j}}/a_{l}}}}}}}$for every parity symbol P_(j), wherein n denotes the length of saidcodeword (c), Λ denotes a polynomial of a degree that is no larger thanthe number of parity symbols in said codeword (c), said polynomial Λbeing independent of said parity symbols P_(j), {a₀, a₁, . . . ,a_(n-1)} is a set of n distinct and non-zero elements of a finite field,Λ′ denotes the first derivative of λ, i_(j) is a positive integerdenoting the position of the j-th parity symbol in said codeword, {y₀,y₁, . . . , y_(n-1)} is a set of n non-zero elements of said finitefield, and ĉ_(l) equals the data symbol at position l of said codewordif l does not denote a position of a parity symbol in said codeword, orequals 0 if l denotes a position of a parity symbol in said codeword.13. The method according to claim 12, wherein said plurality of paritysymbols (P_(j)) are solely defined in terms of the roots of saidpolynomial (Λ) and the position of the parity symbol within saidcodeword.
 14. The method of claim 12, further comprising a step ofpermuting said data symbols (I_(l)) before preparing said codeword (c).15. A non-transitory storage medium storing instructions readable by acomputing device, such that the computing device, when executing saidinstructions, implements the method according to claim
 1. 16. An encoderfor encoding data to be transmitted from a source to a destination overa communication channel by means of an error-correcting code, saiderror-correcting code being defined by a parity check matrix (H) havingor comprising a Vandermonde structure, said encoder comprising: encodingmeans adapted to receive a plurality of data symbols (I_(l)) and toprepare at least one codeword (c) of said error-correcting code, saidcodeword (c) to be transmitted over said communication channel andcomprising said plurality of data symbols (I_(l)) and a plurality ofparity symbols (P_(j)); and pattern selection means adapted to selectone out of a plurality of parity patterns ({i_(j)}_(j=0, . . . , 2t-1)),said parity pattern ({i_(j)}_(j=0, . . . , 2t-1)) determining thepositions at which said parity symbols (P_(j)) are located within saidcodeword (c); characterized in that said encoder is adapted to determinesaid parity symbols (P_(j)) on the basis of said data symbols (I_(l))and said selected parity pattern ({i_(j)}_(j=0, . . . , 2t-1)) byevaluating a polynomial (Λ^((j)), Λ) of a degree that is no larger thanthe number of parity symbols (P_(j)) in said codeword (c); the encodercomprising a first summing circuit (12), a second summing circuit (18),and a third summing circuit (24), said third summing circuit (24)connecting an output line (16) of said first summing circuit (12) to anoutput line (22) of said second summing circuit (18), wherein said firstsumming circuit (12) comprises a plurality of first registers (14, 14′,14″) adapted to hold a plurality of even powers of a primitive element(α) of a finite field and a corresponding number of first coefficients(λ₁, λ₃, λ₅, λ₇), said second summing circuit (18) comprises a pluralityof second registers (20, 20′, 20″, 20″′) adapted to hold a plurality ofodd powers of said primitive element (α) and a corresponding number ofsecond coefficients (λ₀, λ₂, λ₄, λ₆), and said third summing circuit(24) is adapted to add an output of said first summing circuit (12) toan output of said second summing circuit (18).
 17. The encoder accordingto claim 16, wherein said first registers (14, 14′, 14″) and/or saidsecond registers (20, 20′, 20″, 20″′) each comprise a feedback loop (15,15′, 15″; 21, 21′, 21″, 21″′) for said even and odd powers of saidprimitive element (α), respectively.
 18. The encoder according to claim16, additionally comprising interleaving means (76) adapted to permutesaid data symbols (I_(l)) before preparing said codeword (c).
 19. Anencoder for encoding data to be transmitted from a source to adestination over a communication channel by means of an error-correctingcode, said error-correcting code being defined by a parity check matrix(H) having or comprising a Vandermonde structure, said encodercomprising: encoding means adapted to receive a plurality of datasymbols (I_(l)) and to prepare at least one codeword (c) of saiderror-correcting code, said codeword (c) to be transmitted over saidcommunication channel and comprising said plurality of data symbols(I_(l)) and a plurality of parity symbols (P_(j)); and pattern selectionmeans adapted to select one out of a plurality of parity patterns({i_(j)}_(j=0, . . . , 2t-1)), said parity pattern({i_(j)}_(j=0, . . . , 2t-1)) determining the positions at which saidparity symbols (P_(j)) are located within said codeword (c);characterized in that said encoder is adapted to determine said paritysymbols (P_(j)) on the basis of said data symbols (I_(l)) and saidselected parity pattern ({i_(j)}_(j=0, . . . , 2t-1)) by evaluating apolynomial (Λ^((j)), Λ) of a degree that is no larger than the number ofparity symbols (P_(j)) in said codeword (c): the encoder comprising afirst summing circuit (12), a second summing circuit (18), a thirdsumming circuit (24) and an initialization register (60), said firstsumming circuit (12) comprising a plurality of first registers (14, 14′,14″) adapted to hold a plurality of even powers of an element (a_(l)) ofa finite field and a corresponding number of first coefficients (λ₁, λ₃,λ₄, λ₇), said second summing circuit (18) comprising a plurality ofsecond registers (20, 20′, 20″, 20″′) adapted to hold a plurality of oddpowers of said element (a₁) and a corresponding number of secondcoefficients (λ₀, λ₂, λ₄, λ₆), said initialization register (60) adaptedto initialize said first registers (14, 14′, 14″) and said secondregisters (20, 20′, 20″, 20″′) with said even and odd powers of saidelement (a_(l)), respectively, wherein said third summing circuit (24)connects an output line (16) of said first summing circuit (12) to anoutput line (22) of said second summing circuit (18), and is adapted toadd an output of said first summing circuit (12) to an output of saidsecond summing circuit (18).
 20. The encoder according to claim 19,additionally comprising interleaving means (76) adapted to permute saiddata symbols (I_(l)) before preparing said codeword (c).
 21. Anon-transitory storage medium storing instructions readable by acomputing device, such that the computing device, when executing saidinstructions, implements the method according to claim
 6. 22. Anon-transitory storage medium storing instructions readable by acomputing device, such that the computing device, when executing saidinstructions, implements the method according to claim
 9. 23. Anon-transitory storage medium storing instructions readable by acomputing device, such that the computing device, when executing saidinstructions, implements the method according to claim 12.